In general, in a memory array of the DRAM, as shown in FIG. 8, one memory cell MCij is connected at the intersection point of a bit line BLi (or complementary bit line BLi--) installed on each row (or column) and a word line WLj installed on each column (or row). Each memory cell MCij consists of one N-type MOS transistor TRij and one capacitor Cij. Each word line WLj is connected to a word line driver WDj for of each column, and each bit line BLi (complementary bit line BLi--) is connected to a sense amplifier SAi for each row. Also, the structure of part of the memory array show in FIG. 8 is simplified and shown in the figure to make the explanation easy.
In the sense amplifier SAi, a pair of N-type MOS transistors TR1 and TR2 constitute a transfer gate for conditionally connecting the bit line pairs BLi and BLi-- to the sense amplifier SAi. Three N-type MOS transistors TR3, TR4, and T5 constitute a precharge circuit for precharging the bit line pair BLi and BLi-- to a prescribed potential, for example, an intermediate power supply voltage potential (Vcc/2). A pair of P-type MOS transistors TR6 and TR7 and a pair of N-type MOS transistors TR8 and TR9 constitute an amplifying circuit for respectively amplifying presense voltages on the bit line pair to prescribed levels. One pair of N-type MOS transistors TR10 and TR11 constitute a transfer gate for conditionally connecting the bit line pair BLi and BLi-- to data input and output line pair IO and IO--.
FIG. 9 explains the writing or reading of data into and from the memory cell MCij in the memory cell. In a standby state before reading and writing, an equalizer control signal .phi.E is at H level, and any of the N-type MOS transistors TR3, TR4, and TR5 of the precharge circuit is turned on. On the other hand, a precharge feeder VBLR supplies a voltage of Vcc/2 level. Thus, the bit line BLi and the complementary bit line BLi-- is precharged in an equalized (equilibrated or short-circuited) state to Vcc/2 level.
If an external row address strobe signal RAS.sub.-- falls to L level for reading or writing, the equalizer control signal .phi.E falls to L level in response to it, and any of the transistors TR3, TR4, and TR5 of the precharge circuit are turned off.
Next, the word line WLj of a selected column is activated by the word line driver WDj, and the potential information (storage information) of the memory cell MCi,j connected to the word line WLj is read out on one of the bit line pairs, for example, on the bit line BLi, so that the potential of the bit line BLi is changed. In the example of FIG. 9, the potential information is "0," and the potential of the bit line BLi is slightly changed downward from the Vcc/2 level.
Next, one sense amplifier driving line SDN is pulled down to a ground potential Vss, and the other sense amplifier driving line SDP is pulled up to a power supply voltage Vcc.
In this example, since the potential of the bit line BLi is changed downward from the Vcc/2 level, the P-type MOS transistor TR7 is turned on. Thus, the complementary bit line BLi-- is connected to the sense amplifier driving line SDP via the transistor TR7, and the complementary bit line BLi-- is pulled up to the power supply voltage Vcc. On the other hand, the transistor TR7 is turned on, and the voltage of the complementary bit line BLi-- is raised, so that the N-type MOS transistor TR8 is turned on. The bit line BLi is connected to the sense amplifier driving line SDN via the transistor TR8 turned on, and the bit line Bli is pulled down to the ground potential Vss.
Next, if a Y address line YSi is activated by a Y address decoder (not shown in the figure), the transfer gates TR10 and TR11 are turned on, and the bit line BLi and the complementary bit line BLi-- are respectively connected to the data input and output line IO and the complementary data input and output line IO--.
Thus, when reading, the data read out to the bit line BLi from the memory cell MCi,j is sent onto the data input and output line IO via the transfer gates T1[sic; TR1] and TR10. When writing, the data on the data input and output line IO is sent to the bit line BLi via the transfer gates TR10 and TR1 and written into said memory cell (memory cell at the intersecting point of the bit line BLi and the word line WLj).
On the other hand, for example, in a large-scale DRAM such as the 64 Mb class, the memory array in one chip is divided into several blocks or submats, and the memory array constitution, in which the memory array is divided into several unit memory arrays, is adopted in each submat.
In each submat, a fixed number of unit memory arrays is arranged in a matrix form at a fixed interval. Then, a set circuit (word line driver bank) of the word line driver WD is arranged in the vicinity of each unit memory cell, for example, at both the left and right sides so that they face each other. Therefore, a fixed number of unit memory arrays is arranged in one column at a fixed interval in the left and right directions, and the sense amplifier banks corresponding to each unit memory array are arranged in one column at a fixed interval.
One equalizer control line BLEQ for supplying the equalizer control signal .phi.E is allocated to the sense amplifier bank of each column or each row arranged in one column. Each equalizer control line BLEQ is extended so that it crosses horizontally or vertically in the submat from the output terminal of an equalizer control line driver arranged at one end of the submat, distributed via an interlayer insulating film on the sense amplifier bank of each row or each column, and connected via a contact hole to all the sense amplifiers SAi in the sense amplifier bank of each row or each column.
FIG. 10 shows a circuit constitution of the equalizer control line driver used in such a conventional DRAM. The equalizer control line driver consists of a CMOS inverter, and the output terminal is connected to the equalizer control line BLEQ. The input terminal receives a timing signal .phi.A for controlling the equalizer from an array controller (not shown in the figure).
When the equalizer timing signal .phi.A is at the L level, the P-type MOS transistor MP is turned on, and the N-type MOS transistor MN is turned off. The equalizer control line BLEQ is connected to a power supply voltage terminal with a prescribed voltage VDD (for example, 2.9 V) at the H level via the P-type MOS transistor MP in the on state. Thus, the equalizer control signal .phi.E is held at the H level. In each sense amplifier SAi connected to the equalizer control line BLEQ, each N-type transistor TR3, TR4, and TR5 of the precharge circuit is electrified, and the equalizer of the bit line pair BLi and BLi-- is turned on (activated state).
If the equalizer timing signal .phi.A is at the H level, the N-type MOS transistor MN is turned on, and the P-type MOS transistor MP is turned off. The equalizer control line BLEQ is connected to the power supply voltage terminal of the ground voltage Vss via the N-type MOS transistor MN in the on state. Thus, the equalizer control signal .phi.E falls to the L level, and in each sense amplifier SAi connected to the equalizer control line BLEQ, each N-type transistor TR3, TR4, and TR5 of the precharge circuit is blocked, so that the equalizer of the bit line pair BLi and BLi-- is turned off. Thereby, a sensing operation is enabled by the amplifying transistors TR6-TR9.
As mentioned above, in such a of DRAM, as a rule, after lowering the row address strobe signal RAS.sub.-- to the L level, first, the equalizer of the bit line pair BLi and BLi-- is turned off (disabled) by lowering the equalizer control signal .phi.E to the L level, and the selected word line WLj is then activated.
In the procedure, if the timing for activating the word line WL is accelerated, the memory access time (time from the fall of RAS.sub.-- to the data input and output) can be shortened, so that the memory access speed can be improved.
However, even in case the word line WL is raised at a fast timing, the equalizer control signal .phi.E must be lowered to the L level at a speed faster than that. Since both a timing signal for starting the rise of the word line WL and a timing signal for starting the fall of the equalizer control signal .phi.E are generated from a common address decoding signal, there is a limitation in accelerating the timing for starting the fall of the equalizer control signal .phi.E.
Therefore, in order to fit the timing of the equalizer control signal .phi.E to the early activation of the word line WL, the rise speed of the equalizer control signal .phi.E or equalizer control line BLEQ must be improved.
On the other hand, as mentioned above, each equalizer control signal BLEQ is commonly connected to the precharge circuit (TR3, TR4, and TR5) of all the sense amplifiers belonging to several sense amplifier banks on each column or each row in the submat. For this reason, the wiring resistance or wiring capacity of the equalizer control line BLEQ itself is large, and the input gate capacity in the precharge circuit (TR3, TR4, and TR5) is also large, so that the load capacity of the equalizer control line BLEQ is very large.
However, since the conventional DRAM is a system that drives such an equalizer control line BLEQ with a very large load capacity from one end of the submat by the above-mentioned CMOS inverter type equalizer control line driver (FIG. 10), it is difficult to accelerate the fall rate of the equalizer control signal .phi.E. In particular, the larger the separation from the equalizer control line driver, the higher the increase of the delay in the equalizer control line BLEQ, and the slower the fall rate of the equalizer control signal .phi.E.
For this reason, if the activation timing of the word line WL is accelerated, as shown in FIG. 11, a cross point CP, at which the potential of the equalizer control line BLEQ (equalizer control signal .phi.E) and the potential of the word line WL intersect, is inevitably raised, and the word line W is raised up to the level of a threshold or higher while BLEQ (.phi.E) is still higher than the threshold of the precharge circuit (TR3, TR4, and TR5), so that a sensing sufficiency is generated through the precharge circuit, or data in the memory cell is likely to be damaged.
Thus, in the conventional DRAM, since the fall of the equalizer control signal .phi. is slow, if the activation timing of the word line is raised, inconveniences such as sensing insufficiency are likely to occur. For this reason, the improvement of the memory access speed is difficult.
The present invention considers these problems, and its objective is to provide a semiconductor memory device that greatly shortens the required time for turning off a bit line equalizer and can speed up the memory access time.